Intel Unveils Next-Gen Ice Lake-SP Xeon CPUs: 28 Core Die With 10nm+ Sunny Cove Cores Detailed

The 2nd-Generation Intel Xeon Scalable platform provides the foundation for a powerful data centre platform that creates a jump in agility and scalability. Intel Corporation on April 2, 2019, introduced a portfolio of data-centric tools to assistance its customers extract more value from their data. (Credit: Intel Corporation)

Intel has unveiled the details of its adjacent-generation Xeon CPU family unit codenamed Ice Lake-SP at HotChips 32. Coming later this year, Ice Lake-SP CPUs are going to host a range of new features such as a brand new chip compages, improved I/O, and an enhanced software stack powering Intel'southward offset 10nm server lineup.

Intel Water ice Lake-SP 'Adjacent-Gen Xeon' CPUs Detailed - Feature 10nm+ Sunny Cove Cores & Avant-garde Capabilities

The Intel Ice Lake-SP is officially launching later on this yr on the Whitley platform. The platform will scale to unmarried and dual-socket servers. In its presentation, Intel unveiled a 28 cadre Ice Lake-SP CPU every bit an example to demonstrate the enhanced capabilities that Ice Lake-SP offers over Cascade Lake-SP.

Intel has non confirmed if the 28 cadre CPU they showcased is the highest core count that will be available with the Ice Lake-SP family or if at that place would exist higher core count variants. Before rumors do indicate to higher core counts so this 28 core dice could just be used for comparing with the top of the stack 2nd Gen Xeon CPUs bachelor today.

Intel Water ice Lake-SP 'Next-Gen CPU' CPU Architecture

Coming to the details, Intel mentions that its Ice Lake-SP CPUs are made on the 10nm+ process and not the 10nm++ process which is utilized by the Tiger Lake CPUs which launch next month. The Ice Lake-SP family unit will make apply of the Sunny Cove cores which evangelize upward to xviii% IPC increase over the Skylake architecture which all 14nm Xeon CPUs utilise.

Intel's 3rd Gen Xeon Scalable Family unit, Codenamed Water ice Lake-SP, presentation at HotChip 32 (Prototype Credits: HardwareLuxx)

The Sunny Cove architecture, in general, adds a range of improvements over Cascade Lake or the enhanced Skylake cores such equally:

• Improved Front end end: higher chapters and improved branch predictor
• Wider and deeper machine: wider allotment and execution resource + larger structures
• Enhancements in TLBs, single-thread execution, prefetching
• Server enhancements - larger Mid-level Cache (L2) + 2nd FMA

Intel also adds in a range of new SIMD instructions exclusive to the Sunny Cove server processors that are mainly meant to increase performance in Cryptography and compression/decompression workloads. That along with enhanced software and algorithmic support will let Intel gains of upwardly to 8X per cadre over Cascade Lake.

Intel Xeon SP Families:

Family Branding	Skylake-SP	Cascade Lake-SP/AP	Cooper Lake-SP	Water ice Lake-SP	Sapphire Rapids	Emerald Rapids	Granite Rapids	Diamond Rapids
Process Node	14nm+	14nm++	14nm++	10nm+	Intel 7	Intel 7	Intel 4	Intel 3?
Platform Proper noun	Intel Purley	Intel Purley	Intel Cedar Isle	Intel Whitley	Intel Eagle Stream	Intel Eagle Stream	Intel Mountain Stream Intel Birch Stream	Intel Mountain Stream Intel Birch Stream
Core Compages	Skylake	Cascade Lake	Cascade Lake	Sunny Cove	Golden Cove	Raptor Cove	Redwood Cove?	Lion Cove?
IPC Improvement (Vs Prev Gen)	x%	0%	0%	20%	19%	viii%?	35%?	39%?
MCP (Multi-Scrap Parcel) SKUs	No	Aye	No	No	Yes	Yes	TBD (Peradventure Yes)	TBD (Mayhap Yep)
Socket	LGA 3647	LGA 3647	LGA 4189	LGA 4189	LGA 4677	LGA 4677	TBD	TBD
Max Core Count	Upward To 28	Up To 28	Up To 28	Up To 40	Up To 56	Upward To 64?	Up To 120?	Upwardly To 144?
Max Thread Count	Up To 56	Up To 56	Upwards To 56	Up To 80	Upwardly To 112	Upwardly To 128?	Up To 240?	Up To 288?
Max L3 Cache	38.5 MB L3	38.5 MB L3	38.5 MB L3	60 MB L3	105 MB L3	120 MB L3?	240 MB L3?	288 MB L3?
Vector Engines	AVX-512/FMA2	AVX-512/FMA2	AVX-512/FMA2	AVX-512/FMA2	AVX-512/FMA2	AVX-512/FMA2	AVX-1024/FMA3?	AVX-1024/FMA3?
Memory Support	DDR4-2666 6-Channel	DDR4-2933 6-Channel	Up To vi-Channel DDR4-3200	Upwards To 8-Channel DDR4-3200	Upward To 8-Aqueduct DDR5-4800	Up To 8-Channel DDR5-5600?	Up To 12-Channel DDR5-6400?	Upward To 12-Channel DDR6-7200?
PCIe Gen Support	PCIe 3.0 (48 Lanes)	PCIe 3.0 (48 Lanes)	PCIe 3.0 (48 Lanes)	PCIe four.0 (64 Lanes)	PCIe 5.0 (lxxx lanes)	PCIe 5.0 (80 Lanes)	PCIe 6.0 (128 Lanes)?	PCIe 6.0 (128 Lanes)?
TDP Range	140W-205W	165W-205W	150W-250W	105-270W	Up To 350W	Up To 375W?	Up To 400W?	Upwards To 425W?
3D Xpoint Optane DIMM	North/A	Apache Laissez passer	Barlow Pass	Barlow Pass	Crow Laissez passer	Crow Pass?	Donahue Pass?	Donahue Pass?
Competition	AMD EPYC Naples 14nm	AMD EPYC Rome 7nm	AMD EPYC Rome 7nm	AMD EPYC Milan 7nm+	AMD EPYC Genoa ~5nm	AMD Next-Gen EPYC (Post Genoa)	AMD Next-Gen EPYC (Post Genoa)	AMD Next-Gen EPYC (Mail service Genoa)
Launch	2017	2018	2020	2021	2022	2023?	2024?	2025?

Intel Ice Lake-SP 'Next-Gen CPU' 28 Cadre Die & Whitley Platform Detailed

Looking at the block diagram of the Ice Lake-SP 28 cadre CPU, the chip offers a new interconnect in the class of an enhanced Mesh Fabric which runs through all of the 28 CPU cores. The Water ice Lake-SP die features ii 4-channel retentiveness controllers whereas the Cascade Lake-SP die offered two tri-channel memory controllers.

The Intel Ice Lake-SP processors also feature four PCIe Gen 4 controllers, each offers xvi Gen 4 lanes for a total of 64 lanes on the 28 cadre die. The Cascade Lake-SP chips offered hexa-aqueduct memory support while Ice Lake-SP will offering octa-channel retention back up on the Whitley platform at launch. The platform will be able to support upwards to DDR4-3200 MHz memory (16 DIMM per socket with 2nd Gen persistent memory support.

Intel is likewise adding a range of latency and coherence optimizations to Ice Lake-SP chips. Simply you tin can see that the retentiveness bandwidth-latency gets a big jump with the 8-channel memory interface and the higher DIMM speeds.

Intel Water ice Lake-SP 'Next-Gen CPU' New Interconnect Infrastructure

In addition to the standard Mesh interconnect, Intel has farther expanded its interconnect design for Ice Lake-SP Xeon CPUs. The new control fabric and data cloth do connect with the cores and different controllers of the bit but besides manage the information flower and power command for the chips themselves. These new interconnects will deliver even lower latency and faster clock updates than 3rd Gen Cooper Lake-SP fries. For example, the core frequency transition takes 12us and the mesh frequency transition takes 20us on Cascade Lake-SP chips. Ice Lake-SP in comparison takes less than 1us and 7us, respectively.

The less frequency drain ways higher efficiency over Cascade Lake. Ice Lake-SP will likewise improve upon the AVX frequency since not all AVX-512 workloads consume college power. This too isn't specific to just AVX-512. Even AVX-256 instructions on Water ice Lake-SP will evangelize improve frequencies contour over Cascade Lake CPUs.

Some of the major upgrades that 10nm volition deliver include:

• two.7x density scaling vs 14nm
• Self-aligned Quad-Patterning
• Contact Over Active Gate
• Cobalt Interconnect (M0, M1)
• 1st Gen Foveros 3D Stacking
• 2nd Gen EMIB

The Intel Ice Lake-SP lineup would be directly competing against AMD'southward enhanced 7nm based EPYC Milan lineup which will feature the brand new 7nm Zen 3 core compages which is confirmed to exist i of AMD's biggest architectural upgrade since the original Zen cadre. Expect to see more Intel & NVIDIA based servers in the coming months.

Source: https://wccftech.com/intel-unveils-ice-lake-sp-xeon-cpu-family-10nm-sunny-cove-cores-28-core-die/

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